In modern CMOS chip designs, as devices have scaled into a regime with channel lengths below 50 nm, the heat generated by switching of digital logic gates or by their leakage, can no longer be efficiently dissipated through the substrate. Recent developments in silicon technology have exacerbated this issue, while at the same time, interconnect reliability is becoming increasingly subject to electro-migration stress in advanced technology nodes due to a breakdown in the classical scaling of such devices.
Supplying and dissipating power in a chip has been a module and chip design issue. Scaled CMOS design devices with higher power density are hot, especially with large, multi-finger FETs. Self-heating of devices during normal circuit operation is becoming significant and could cause Back End of the Line reliability and Electro Migration wear out issues. This issue of device self-heating is getting worse as technology scales. Preliminary CAD simulations and hardware temperature measurements show a 2× increase in deltaT (i.e., a temperature change from ambient) going from 22 nm to 14 nm technology nodes. In order to maintain reliable operation of a chip there is a need to maintain the temperature increase at an acceptable range.
Localized self heating in which heat is dissipated through devices, wires and substrate is a serious concern that must be managed across IP types by the design methodology in high-performance chip design.